1. Field of the Invention
Exemplary embodiments of the present invention relate to a composition for removing an insulation material, and related methods. In particular, exemplary embodiments of the present invention relate to a composition for removing an insulation material that may effectively remove a low-k film and a protection film with reduced damage to a substrate on which the films are formed, a method of removing an insulation layer, and a method of recycling a substrate.
This application claims priority to Korean Patent Application No. 2005-72471, filed on Aug. 8, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
A demand for semiconductor devices having greater integration densities and higher operating speeds has existed throughout the decades long development of various information processing apparatuses. Thus, developments in semiconductor device fabrication technologies have been directed towards increasing integration, improved reliability, and obtaining higher operating speeds.
As integration densities for semiconductor devices have increased, the respective design rules for semiconductor devices have decreased. Contemporary design rules include, for example, wiring widths of about 100 nm or less. However, as design rules have decreased, RC delay times have increased for wirings and other elements formed according to the decreased design rules. An RC delay time is determined in accordance with the resistance (R) of (e.g.,) a wire and the capacitance (C) of an insulation layer disposed between adjacent wires. An increased RC delay time causes a reduction in semiconductor device operating speed. Therefore, to obtain a semiconductor device having greater integration density and a fast operating speed, either the resistance of the wiring or the dielectric constant (k) of the insulation layer must be reduced.
To reduce the wiring resistance, a conductive material having a low resistivity has been used to form the wiring. For example, a fabrication process has been developed that forms wiring from copper instead of aluminum, since copper has a substantially lower resistivity than aluminum.
An insulation material having a low dielectric constant is also useful in achieving a reduced RC delay time. In a conventional semiconductor device, the insulation layer is generally formed from silicon oxide having a dielectric constant of about 3.9. As the thickness of the insulation layer is reduced, a silicon oxide insulation layer does not effectively isolate adjacent wires, and parasitic capacitance may form between adjacent wires. Therefore, low-k materials having a dielectric constant substantially lower than that of silicon oxide have been developed.
The low-k materials generally have a dielectric constant less than or equal to about 3. Low-k materials may generally be divided into organic low-k materials and inorganic low-k materials, but organic low-k materials are more commonly used in conventional practice. Carbon-doped silicon oxide (SiOCH), silicon oxycarbide(SiOC), hydrogenated silicon oxide (SiOH), BLACK DIAMOND™, methylsilsesquioxane (MSQ), fluorinated silicate glass (FSG), organic silicate glass (OSG), etc., are examples of organic low-k materials.
When an insulation layer is formed using low-k material, the insulation layer may be easily damaged by plasma based fabrication processes subsequently applied to semiconductor devices, such as those commonly used in dry etching processes. Furthermore, the insulation layer formed using low-k material may be porous. A porous insulation layer readily absorbs moisture through the pores, which deteriorates the insulation layer. Thus, a protection layer is generally formed on the insulation layer to prevent deterioration of the insulation layer. The protection layer is formed from a substance such as silicon carbonitride (SiCN), silicon nitride (SiN), silicon carbide (SiC), etc. Additionally, the protection layer may be used as a capping layer formed on a conductive material.
Between and among the lengthy sequence of fabrication processes necessary to form semiconductor devices on a wafer, various inspection processes are performed. For example, when processing a wafer, each process performed on the wafer may also be performed on a dummy wafer, so that, after each process is performed, the thickness and characteristics of a layer formed on the wafer may be estimated using the dummy wafer.
Once a dummy wafer has been used, it may be recycled through a recycling process or discarded; however, recycling the dummy wafer is economically advantageous. This is particularly true of late as commercial wafers have diameters of about 300 mm. These very large wafers are expensive and, thus, recycling dummy wafers become more necessary.
When forming a low-k material layer and/or a protection layer on a wafer, a dummy wafer is used along side the wafer. After performing an inspection process on the dummy wafer, the low-k material layer and/or the protection layer may then be removed from the dummy wafer.
The low-k material layer and/or the protection layer are removed through a dry etching process or a wet etching process. A dry etching process may be performed using plasma, and a wet etching process may be performed using an etching solution. For example, U.S. Patent Publication No. 6,890,391, discloses a method for removing a low-k material layer and a protection layer using a dry etching process. In the disclosed method, the low-k material layer is formed from silicon oxide, methylsilsesquioxane (MSQ), hydrosilsesquioxane (HSQ), silicon oxycarbide (SiOC) or carbon-doped silicon oxide (SiOCH), and the protection layer is formed using silicon nitride (SiN) or silicon carbonitride (SiCN). Also, Japanese Laid-Open Patent Publication No. 2001-65459 discloses a method of dry etching a low-k material layer comprising silicon oxycarbide (SiOC) using a mixture gases comprising fluorinated carbon gas, nitrogen gas, and an inert gas having a flow rate greater than or equal to about 80%. In addition, Korean Laid-Open Patent Publication No. 2004-102981 discloses a method of removing an insulating interlayer through a plasma etching process using a mixture gas of CF4/O2/Ar. In the disclosed method, the insulating interlayer comprises an oxide layer, an organic low-k material layer, an organic porous low-k layer, or a combination thereof.
In the above methods of removing the low-k layer and/or the protection layer through a dry etching process, plasma having a high energy level damages the layer underneath the low-k layer and/or the protection layer. Furthermore, recycling a dummy wafer from which a low-k layer and/or a protection layer has been removed using a dry etching process is not economically advantageous.
Korean Laid-Open Patent Publication No. 2002-55888 discloses a method of manufacturing a metal wiring and a capacitor in a semiconductor device. In the disclosed method, an insulation layer formed using silicon oxide, fluorinated silicate glass (FSG), carbon-doped silicon oxide (SiOCH), silicon oxycarbide (SiOC), or hydrogenated silicon oxide (SiOH) is removed using a hydrogen fluoride solution. However, the hydrogen fluoride solution does not sufficiently remove the low-k material from the object on which it is formed. Furthermore, the hydrogen fluoride solution etches a protection material such as silicon carbonitride (SiCN) very little.
Japanese Laid-Open Patent Publication No. 2002-246378 discloses a method of selectively etching a silicon nitride layer and a silicon oxynitride layer using an etching solution relative to a silicon wafer or a silicon oxide layer. In the disclosed method, the etching solution comprises sulfuric acid, ammonium fluoride (or hydrogen fluoride), and less than or equal to about 5 percent by weight of water. The etching process is performed at a temperature greater than or equal to about 150° C. Furthermore, the etching solution comprises excessive sulfuric acid. Thus, etching rates of the silicon nitride layer and the silicon oxynitride layer are not easily controlled, and the stability of the etching solution is reduced.
The subject matter of these background documents is hereby incorporated by reference.